In addition to weekly meetings of students with their supervising assistant, we make it a habit to have all student designs reviewed by a small team of senior designers and/or lecturers half-way through the design process. Our intentions are as follows:

• Learn about the project status
• Discuss major design decisions
• Make a few sanity checks
• Take corrective action if necessary (downsize, intensify support, change process, or alike)

• Plan for fabrication via multi-project wafer (MPW) service

One hour is normally set aside for each student project. Please be prepared to show and explain the subsequent items even if they are of preliminary nature at the time of the review.

• Mission of your target design
• Results from software models and/or important simulation runs
• Human-readable block-diagrams at architecture level
• Clock domains with clocking discipline and clock frequency
• List of all pins including inputs, outputs, power and ground
• Anticipated circuit size in gate equivalents
• Test concept and test structures
• Important open issues

We encourage all the design students to progress through all the design steps (synthesis, preparing a test solution, placement and routing) to get familiar with the tools and setup with an early (not complete) version of your design. We will ask for the following specific outputs from you during the design review:

• The result of the 'elaborate' command in synopsys
• The 'tmax.log' that is generated after a Tetramax run
• The floorplan of the design in SoC encounter (power routing, placement of Macro blocks, placement of I/O cells).

Designreviews schedule: to be announced