Examples of Verilog models

Combinational circuit models

Mealy, Moore, and Medvedev machines

A Mealy-type state machine

A Moore-type state machine

A Medvedev-type state machine

State reduction and state encoding

Simulation testbenches

A testbench of grade 1

A testbench of grade 2

Note: Under Unix the TAR-archives can be unpacked with:

tar -xvf archive.tar